Jennifer Dworak, Ph.D.

Dr. Jennifer Dworak

Jennifer Dworak, Ph.D.

Professor of Electrical and Computer Engineering
Professor of Computer Science (by Courtesy)

Office Location: Junkins 337

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Education

  • Texas A&M University, Ph.D. in Electrical Engineering
  • Texas A&M University, MS in Electrical Engineering
  • Texas A&M University, BS in Electrical Engineering

Biography

Jennifer Dworak is a Professor in the Department of Electrical and Computer Engineering at SMU Lyle. Her research interests include manufacturing test, hardware security, silent data corruption, and the reliability of digital circuits and systems. She is a recipient of an NSF CAREER Award and a 2012 Ralph E. Powe Junior Faculty Enhancement Award funded by Oak Ridge Associated Universities. She is a co-author on multiple technical articles, including two papers that won Best Paper Awards from the VLSI Test Symposium and a paper that won a TTTC Naveena Nagi Award. Prof. Dworak also holds two patents on cybersecurity locks, keys, traps and honeypots and a patent on a laser-powered device for enhanced security. She has given over 30 invited talks and been an invited panelist at multiple technical meetings, including meetings in North and South America and in Europe.

Honors and Awards

  • Best Paper Award, VLSI Test Symposium, Dana Point, CA, 1999 (announced in 2000)

  • National Science Foundation Graduate Research Fellowship, 2000 - 2003

  • Best Student Presentation Award, International Test Synthesis Workshop, March 2002

  • TTTC Naveena Nagi Award presented at the 2004 VLSI Test Symposium, April 2004

  • NSF CAREER Award, March 2010

  • Ralph E. Powe Junior Faculty Enhancement Award, Oak Ridge Associated Universities, April 2012

  • Speaker at Special Session that won the “Best Innovative Practices Award” for a Session on Protocol-Aware Testers at the 2012 VLSI Test Symposium. Awarded April 29, 2013

  • IEEE Excellence in Design and Test Engineering Award, Awarded to paper entitled:
    “Using Existing Reconfigurable Logic in 3D Die Stacks for Test,” and published
    at the North Atlantic Test Workshop. Awarded May 10, 2016

  • Organizer for Special Session that won the “Best Special Session Award” for the Hot Topic Session: Future Extensions of IEEE Test Standards presented at the 2017 VLSI Test Symposium. Awarded April 23, 2018

  • Invited Keynote Speaker: “Watch the Back Door: Security Issues in Test,” Presented at the TESTA Workshop associated with the European Test Symposium, Bremen, Germany, June 1, 2018

  • Best Paper Award, VLSI Test Symposium, Monterey, CA, 2019 (announced in 2020)

  • Invited Keynote “Circuit Structures for Enhancing Efficient Defect Detection,” 1st Workshop on Data Integrity and Secure Cloud Computing (DISCC 2022)

  • Associated with the 55th International Symposium on Microarchitecture
    (MICRO 2022), October 2, 2022

Research

  • Reliability of Integrated Circuits and Systems
  • Manufacturing Test and Design for Testability (DFT)
  • Silent Data Corruption
  • Hardware Security
  • Hardware Trojans
  • Power Analysis Attack Mitigation

Publications

  • S. Gupta, B. Bhaskaran, S. Sarangi, A. Abdollahia, and J. Dworak, “A Novel Graph Coloring Based Solution for Low-Power Scan Shift,” 2019 IEEE VLSI Test Symposium, April 2019. (Winner of Best Paper Award)
  • David Brauchler and Jennifer Dworak, “Multi-Level Access Protection for Future IEEE P1687.1 IJTAG Networks,” IEEE International Test Conference, November 2020.
  • Y. Sun, H. Jiang, L. Ramakrishnan, J. Dworak, K. Nepal, T. Manikas, and, R. I. Bahar, "Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits," 2021 IEEE International Test Conference (ITC), 2021, pp. 319-323, doi: 10.1109/ITC50571.2021.00045.
  • H. Jiang, J. Dworak, K. Nepal, T. Manikas, “Enhanced DFT for Fortuitous Detection of Transition Faults During Scan Shift,” IEEE 31st Microelectronics Design & Test Symposium (MDTS), May 2022
  • S. Yassein, H. Jiang, J. Dworak, K. Nepal, and T. Manikas, “Harvesting Wasted Clock Cycles for Efficient Online Testing,” IEEE European Test Symposium (ETS), to be held May 2023.